Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and a thin oxide liner is thermally grown on the trench walls. The trench is then refilled with a thick insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor. The quality and thickness of the gate oxide are crucial to the performance of the finished device.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality and to round the trench comer. The trench is then refilled with an insulating material (or "trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop. In subsequent operations, the nitride and pad oxide are stripped off, and a gate oxide layer is grown on the exposed silicon of the substrate.
Disadvantageously, the gate oxide layer typically does not grow uniformly. Rather, it tends to be thinner at the trench edges, because the gate oxide growth rate is smaller there due to the sharpness of the trench edges and the different crystallographic orientation of the silicon at the trench edges. The thinness of the gate oxide and the sharpness of the trench edges increase the electric field strength at the trench edges, thereby decreasing device reliability.
In copending application Ser. No. 08/993,858, a method is disclosed for forming trench isolation wherein an oxide layer at the trench corners is thick and rounded. The disclosed methodology comprises growing a pad oxide layer on the substrate, then applying a photoresist mask directly on the pad oxide layer to define the trench areas. The exposed portions of the pad oxide layer are etched away, and the etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the pad oxide layer, and the substrate is oxidized to form an oxide liner on the walls, base and top edges of the trench. A polish stop such as a nitride is then applied over the pad oxide and oxide liner. Next, the trench is refilled with an insulating material, and planarized down to the nitride polish stop. FIG. 1 illustrates an STI structure formed by this methodology and comprising substrate 100, pad oxide layer 102, trench 104 with trench edge 104a, liner oxide 106, polish stop 108, and insulating material 110. Since the liner oxide 106 is formed directly on the trench edge 104a without the restraint of a nitride polish stop, it grows thick and rounded, and upon removal of the nitride polish stop 108 over the active area 100a by anisotropic etching, remains over the trench edge 104a, thereby contributing to the improvement of the quality of the subsequently grown gate oxide.
The methodology disclosed in copending Application Serial No. 08/993,858 contributes to solving the problems of thin gate oxide at the trench edges and sharpness of the trench edges, thereby reducing the electric field between the gate electrode and substrate in proximity to the trench edges and improving gate oxide quality. However, as a result of this methodology, the nitride polish stop 108 remains in the trench 104 upon completion of the STI structure. The presence of the nitride polish stop 108 in the trench 104 is potentially disadvantageous due to the high dielectric properties of the nitride polish stop 108, which can cause unwanted electrical effects, such as low field threshold voltages at the bottom of the trench 104 and transistor edge leakage at the trench edge 104a.
There exists a continuing need for shallow trench isolation methodology wherein the resulting gate oxide layer at the trench edges exhibits high reliability without unwanted electrical effects.